In recent years, the camera industry has been experiencing the rapidly ongoing technology transition from analog to digital devices. The market of digital still cameras which require no film development, in particular, is roaring and attracting consumers. Most of mobile telephones selling now are camera-equipped telephones, and pixels and image processes increasingly upgraded in digital still cameras are contributing to remarkable improvements of an image quality.
The digital camera is conventionally embedded with an analog front-end device (large-scale semiconductor integrated circuit). The analog front-end device converts an image signal (analog electric charge signal) outputted from a solid image sensor into digital data adapted to the analog electric charge signal and outputs the digital data.
The digital data outputted from the analog front-end device is subjected to a variety of image processing tasks, for example, luminance signal processing, color separation processing, and color matrix processing, executed by a signal processing circuit such as DSP (digital signal processor). The solid image sensor, DSP, and analog front-end device are configured of semiconductor integrated circuits, and the semiconductor integrated circuits are mounted on a printed wiring board.
Referring to FIG. 21, conventional problems of the imaging system (such as electronic still camera or video camera) are described. The imaging system has a CCD (charge coupled device) 91 used as an imaging device, an AD conversion LSI 92, and a DSP 93. The CCD 91, AD conversion LSI 92, and DSP 93 are configured of semiconductor integrated circuits, and semiconductor integrated circuits are mounted on a printed wiring board 100. The CCD 91 outputs an analog image signal obtained when the CCD 91 captures an image and outputs the obtained analog image signal to the AD conversion LSI 92. The AD conversion LSI 92 converts the analog image signal inputted thereto into a digital signal, and outputs the digital signal to the DSP 93. The DSP 93 image-processes the digital signal inputted thereto and displays the image-processed digital signal on a display 101.
The AD conversion LSI 92 is connected to the DSP 93 on the printed wiring board 100 with printed wiring routed thereon. When the image data generated by the AD conversion LSI 92 is transmitted to the DSP 93 by way of the printed wiring, a power supply noise occurs. The power supply noise penetrates into the CCD 91 through power supply lines (Vcc and ground) on the printed wiring board 100. Then, the power supply noise infiltrates the analog image signal outputted from the CCD 91 and inputted to the AD conversion LSI 92. The power supply noise thus introduced into the AD conversion LSI 92 is transmitted outside through an output terminal of the LSI 92 and then reenters the LSI 92 through an input terminal thereof by way of the power supply lines and a semiconductor substrate.
Because of the factors described below, the power supply noise results in a relatively large value.                When the digital signal is outputted from the AD conversion LSI 92, there is a large through current or load drive current at the time of bit change.        An LSI output unit conventionally generates a relatively large output current.        
Because the AD conversion LSI 92 is provided with an amplifier such as PGA (programmable gain control amplifier) which amplifies an inputted analog signal, the power supply noise is unavoidably amplified by the amplifier alongside the image signal. The noise thus amplified appears on a display screen, deteriorating the quality of a displayed image.
Though a possible solution for the noise is to connect a pass capacitor having a large capacity to the power supply terminal of the AD conversion LSI, it is not a decisive solution for any noise-associated problems. On top of that, there are unfavorable events brought by the solution; a chip size increase and deterioration of a packaging efficiency.
An AD conversion LSI 80 illustrated in FIG. 16 is a device disclosed in Unexamined Japanese Patent Publication No. 2002-300591, which was developed to solve the technical disadvantage described so far.
The AD conversion LSI 80 has a CDS (correlated double sampling circuit) 81, a PGA 82, an AD converter (ADC) 83, an encoder/code converter 84, and an output buffer 88. The CDS 81 performs a sampling process to an analog image signal transmitted from a CCD 70. The PGA 82 variably controls an amplification gain relative to the sampling signal. The ADC 83 converts the amplified analog signal into a digital signal. The encoder/code converter 84 differentiates the AD-converted digital image data and converts the resulting digital image data into gray code. The output buffer 83 outputs the code-converted signals outside of a chip.
The AD conversion LSI 80 is provided with the encoder/code converter 84 between the AD converter 83 and the output buffer 88, which is materially different to the illustration of FIG. 21. The gray code is a binary numeral representation of integral numbers, where there is always only one bit changing position in the binary numeral representation when an original integral number changes by 1.
The encoder/code converter 84 calculates a differential between codes of adjacent pixels involved with the same color after the AD conversion, and converts the differentiated output code into a code with less number of changing bits in switching between the codes such as gray code. Such a code conversion reduces a through current and a load drive current in an output unit, thereby reducing any noise energy associated with output variation.
A typical code converting means used as the encoder/code converter 84 is a binary-gray code converter which converts the inputted binary code into the gray code. The prior art described so far places an emphasis on the technical characteristic that “the differentiated output code targeted for the reduction of changing bits represents the differential between codes of adjacent pixels involved with the same color after the AD conversion”, more specifically, “pixels involved with the same color”.
According to the Bayer array, R (red) and G (green) pixels are arranged on a line in the sequence of R, G, R, G, R, G, . . . , and B (blue) and G (green) pixels are arranged on another line in the sequence of G, B, G, B, G, B, . . . .
The “differential between codes of adjacent pixels involved with the same color” in the former sequence is:    ΔR3−1=(R data value in third row)−(R data value in first row);    ΔR5−3=(R data value in fifth row)−(R data value in third row); and    ΔR7−5=(R data value in seventh row)−(R data value in fifth row).
The “differential between codes of adjacent pixels involved with the same color” in the latter sequence is:    ΔG4−2=(G data value in fourth row)−(G data value in second row);    ΔG6−4=(G data value in sixth row)−(G data value in fourth row); and    ΔG8−6=(G data value in eighth row)−(G data value in sixth row).
These formulas are used to extract changes in the gradation of the same color along a horizontal direction as differential information. A conventional AD-converted signal represents data where two different color data are each repetitive at every other pixel. Therefore, a differential between data of the same color at alternate pixels is obtained in the system described earlier.
FIG. 17 illustrates a structure of the encoder/code converter 84. The encoder/code converter 84 has a delay unit 85, a subtraction unit (differentiator) 86, and a binary-gray code converter 87. The delay unit 85 delays the data outputted from the AD converter 83 by a given clock cycle. The subtraction unit (differentiator) 86 calculates a differential between the data outputted from the AD converter 83 and the data delayed by the delay unit 85. The binary-gray code conversion device 87 converts binary data obtained by calculating the differential into the gray code.
FIG. 18 illustrates specific steps of the differential calculation and the binary data—gray code conversion. An amount of the delay by the delay unit 85 is equal to two cycles of a sampling clock of the CDS 81. The set delay amount is thus equal to two cycles to obtain the data differential of the same color at every other pixel.
An example is given below, in which R and G signals are inputted to the encoder/code converter 84 in turns as illustrated in A) of FIG. 18, and the AD conversion value of each signal changes (base 10) as illustrated in B). C) of the drawing shows the binary codes actually outputted. According to the prior art, these codes were directly outputted. D) of the drawing illustrates number of changing bits when each code switches to a next code as a result of comparison of the adjacent pixels. The number of changing bits in the switching of codes is calculated by the following formulas:    ΔGR2−1=(G data value in second row)−(R data value in first row);    ΔRG3−2=(R data value in third row)−(G data value in second row);    ΔGR4−3=(G data value in fourth row)−(R data value in third row);    ΔRG5−4=(R data value in fifth row)−(G data value in fourth row);
The subtraction unit 86 receives the binary codes of C) inputted from the AD converter 83. The subtraction unit 86 calculates a differential between the data values of the same color in adjacent pixels, that is, a differential between alternate data values as illustrated with curbed arrows in B). Similarly to the description given earlier, the differential is calculated by the following calculation formulas.    ΔR3−1=(R data value in third row)−(R data value in first row);    ΔG4−2=(R data value in fourth row)−(G data value in second row); and    ΔR5−3=(R data value in fifth row)−(R data value in third row).    ΔG6−4=(G data value in sixth row)−(G data value in fourth row).
An initial data is directly used without differential calculation. The value outputted from the subtraction unit 86 results in values of E) when expressed in base 10, and values of F) when expressed in binary code.
The binary-gray code converter 87 converts the differential binary codes in F) into the gray codes as illustrated in G). A downward bold arrow represents the binary-gray code conversion.
G) illustrates the number of changing bits in the switching of codes when adjacent pixels are compared to each other. Comparing D) and H), a smaller number of bits change in the switching of codes in the AD conversion LSI 80 than in the AD conversion LSI 92. The number of changing bits in the switching of codes in total (4, 4, 4, 5, 6, 5, 4) is “32” in the AD conversion LSI 92, while the number of changing bits in the switching of codes in total (4, 4, 0, 2, 1, 1, 1) is “13” in the AD conversion LSI 80. Thus, a tangible improvement in the AD conversion LSI 80 is confirmed.
Because the AD conversion LSI 80 calculates the differential of the same color and converts it into the gray code, there is no large variability between the differentials thereby calculated in adjacent pixels of different colors. Therefore, the number of changing bits when, for example, the output of R (red) image data is switched to the output of G (green) image data is relatively small.
The significance of the binary-gray code conversion is described below. If the differential is calculated but is not subjected to the binary-gray code conversion, the following problem remains unsolved. In a screen, there are plus and minus differentials by a substantially equal ratio. The binary code is expressed by the complement of 2. When the binary code changes from positive to negative, “0” unexceptionally changes to “1”. When the binary code changes from negative to positive, “1” unexceptionally changes to “0”. Once the binary code is converted into the gray code, the code variation is lessened when the binary code changes from positive to negative or vice versa.
For reference, a description is given to a relationship between the gray code and the binary code expressed by the complement of 2. In three-bit binary code, “000” changes to “111” when “0” changes to “−1” in base 10. In any other binary codes of four bits, eight bits, or larger bits, “0” similarly changes to “1”, in which case all of the bits (three bits) change. On the other hand, when “0” changes to “−1” in base 10 in three-bit gray code, “000” changes to “100”, in which case the changing bit is only one bit. Therefore, a through current flow generated at the time of output change in the output buffer is significantly reduced by outputting the gray code as compared to the binary code.
There is no abrupt change between adjacent pixels in any image signals, therefore, there is only a small number of changing bits between pixels of the same color when the code is converted into the gray code immediately after the AD conversion. The prior art does not immediately perform the gray code conversion but calculates the differential beforehand because of a relatively large code difference between different colors of a pixel in any image signals when the CCD output is transmitted through a color element array filter in contrast to a small change between adjacent pixels. An exception is gray color having little color variation in a subject to be imaged, in which there is only a small code difference between different colors. FIG. 20 illustrates a configuration of a conventional gray binary differential decoder 90 used on the reception side. The conventional gray binary differential decoder 90 has a gray binary code converter 91, an adder 92, and a delay unit 93.
Patent Document 1: Unexamined Japanese Patent Publication No. 2002-300591